The present invention relates to multiplication units and methods for operating same, and in particular to such units and methods for multiplying n-place binary numbers such as in a signal processor.
It is an object of the present invention to provide a multiplication unit having a high working speed which requires only one n-place arithmetic unit and one n-place accumulator for multiplying n-place binary numbers represented in two's compliment.
The above object is inventively achieved in a multiplication unit having a rist register containing the multiplicand, and accumulator which accepts intermediate sums, an arithmetic unit for undertaking step-by-step logical combination of the multiplicatand with the intermediate sum contained in the accumulator, with the operand inputs of the arithmetic unit being connected to the first register and to the accumulator. The operations undertaken by the arithmetic unit are defined by the bits of a multiplier which is contained in a second register, the outputs of which are connected to an operation instruction input of the arithmetic unit through a multiplexer and a logic circuit. The multiplexer through-connects the bits of five adjacent multiplier places from the second shift register to the inputs of the logic circuit. One output of the logic circuit is connected to the operation instruction input of the arithmetic unit, and a second output of the logic unit is connected to a control input of a means for shifting the logic operation results, this means in one embodiment being a multiple shift unit connected between the output of the arithmetic unit and the input of the accumulator.
The above multiplication unit and the method for operating same disclosed and claimed herein achieve a particularly high working speed by using only one n-place multiple shift unit for shifting the logical operation results which are supplied as an output by the arithmetic unit to the accumulator.